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| module stage1(
input Clk, //50 Hz clock
input x0,
input reset,
output reg y0,y1,y2,y3,y5,y7,y10,y15,
output reg stage1_done
);
reg [15:0] counter = 0;
parameter F = 50;
always@ (posedge Clk or posedge reset)
if(reset) begin
counter <= 0;
{y0,y1,y2,y3,y5,y7,y10,y15} <= 8'b00000000;
stage1_done <= 0;
end else begin
if(x0 == 1) begin
if(counter == 18*F)
stage1_done <= 1;
else begin
counter <= counter + 1;
stage1_done <= 0;
end
if(counter >= 1*F && counter < 10*F)
y0 <= 1;
else
y0 <= 0;
if(counter >= 1*F && counter < 17*F)
y1 <= 1;
else
y1 <= 0;
if(counter >= 1*F && counter < 9*F)
y2 <= 1;
else
y2 <= 0;
if(counter >= 11*F && counter < 16*F)
y3 <= 1;
else
y3 <= 0;
if(counter >= 1*F && counter < 18*F)
y5 <= 1;
else
y5 <= 0;
if(counter >= 1*F && counter < 5*F)
y7 <= 1;
else
y7 <= 0;
if(counter >= 1*F && counter < 5*F)
y10 <= 1;
else
y10 <= 0;
if((counter >= 2*F && counter < 9*F) || (counter >= 13*F && counter < 7*F))
y15 <= 1;
else
y15 <= 0;
end
end
endmodule
module stage2(
input x0,
input Clk, //50 Hz clock
input reset,
output reg y1,y3,y5,
output reg stage2_done
);
reg [15:0] counter = 0;
parameter F = 50;
always@ (posedge Clk or posedge reset)
if(reset) begin
counter <= 0;
{y1,y3,y5} <= 3'b000;
stage2_done <= 0;
end
else begin if(x0 == 1) begin
if(counter == 8*F)
stage2_done <= 1;
else begin
counter <= counter + 1;
stage2_done <= 0;
end
if(counter >= 1*F && counter < 8*F)
y1 <= 1;
else
y1 <= 0;
if(counter >= 1*F && counter < 8*F)
y3 <= 1;
else
y3 <= 0;
if(counter >= 1*F && counter < 8*F)
y5 <= 1;
else
y5 <= 0;
end
end
endmodule |