I have the verilog code for the sigma delta modulator and the PLL circuits in Cadence. How can I run the co-simulation on the whole PLL including the PLL circuits and the verilog code?
You might want to know simulation environment, SpectreVerilog.
In case of high level simulation, you can model analog part
with VHDL-A.
It can also perform gate level simulation in case your analog part
is described down to transistor. In which case, the computational speed
looks slow to me.