How to replicate a design 500 times using VHDL?

[lahrach]

Hello friends,

I want replicate a design 500 times in order to occupy all the FPGA area, how can I do it with VHDL ?

the port map of 500 designs is a tedious operation!

best regards

 

[FvM]

Re: VHDL trick

Should be easy using vectored port signals and a generate statement in the architecture.

 

[lahrach]

Re: VHDL trick

hi FvM

Can u give more explanations if it is possible can u give an example with a design replicated 4 times.

FL

 

[TrickyDicky]

Re: VHDL trick

package top_ent_package is
  type data_array_t is array(0 to 3) of std_logic_vector(7 downto 0);
end package;

entity top_ent is
 port (
  TOP_ip    : in data_array_t;
  TOP_op    : out data_array_t
 );
 
end entity top_ent;

architecture rtl of top_ent is
begin
  
  ents_gen : for i in 0 to 3 generate
  
    my_inst : some_entity
    port map (
      input    => TOP_ip(i),
      output   => TOP_op(i)
    );
  
  end generate ents_gen;
  
end architecture rtl;

This generates 4 entities with each one being connected to a separate input and output