how to remove unused flipflop duing synthesis

[maverick_mind]

hdlin_preserve_sequential

I have a module with some sequential elements. During actual module usage the path through sequential elements is never exercised.

I want to remove flip flops during synthesis. I tried using set_case_analysis and putting mux select and clock value to 0. But dc still puts flip-flops even though with values of set_case_analysis those path will never be used.

Any solution to remove ff.

PSEUDO-CODE

port (inp, clk, sel: in std_logic;
out: out std_logic);

signal inp_d;

process (inp, clk)
begin
if (clk'event and clk ='1')
inp_d <= inp;
end if;
end process;

out <= inp when sel ='0' else inp_d;
end


in actual situation sel is always '0' so out<=inp. but dc never removes ff.

 

[dcreddy1980]

synthesis set_case_analysis

I have a module with some sequential elements. During actual module usage the path through sequential elements is never exercised.

I want to remove flip flops during synthesis. I tried using set_case_analysis and putting mux select and clock value to 0. But dc still puts flip-flops even though with values of set_case_analysis those path will never be used.

Any solution to remove ff.

PSEUDO-CODE

port (inp, clk, sel: in std_logic;
out: out std_logic);

signal inp_d;

process (inp, clk)
begin
if (clk'event and clk ='1')
inp_d <= inp;
end if;
end process;

out <= inp when sel ='0' else inp_d;
end


in actual situation sel is always '0' so out<=inp. but dc never removes ff.

The DC will default will remove all the unused flipflops or latches and if it has not removed them then it might be due to the below variable :

set hdlin_preserve_sequential false

Regards,
dcreddy