I've just finished to create a block inside my project, but before connecting it to the i/o pins I would like to use some registers between this block and the pins above mentioned. How it is possible to do it? Input and Output can be handled in the same way?
I have already created a signal for each i/o of the block. Which is next step?
create an internal signal and register it, like you would in any HDL:
(VHDL example)
Code:
io_reg_proc : process(clk)
begin
if rising_edge(clk) then
input_reg <= input;
end if;
end process;
my_ent : entity work.my_entity
port map (
data <= input_reg,
--etc
);
Of course, you could just have registers inside my_entity. Any decent synthesisor should place the register next to the IO in the IO buff, otherwise you can usually tell it to do so via assignments.
create an internal signal and register it, like you would in any HDL:
(VHDL example)
Code:
io_reg_proc : process(clk)
begin
if rising_edge(clk) then
input_reg <= input;
end if;
end process;
my_ent : entity work.my_entity
port map (
data <= input_reg,
--etc
);
Of course, you could just have registers inside my_entity. Any decent synthesisor should place the register next to the IO in the IO buff, otherwise you can usually tell it to do so via assignments.
perfect, I understood. in this way I create a registered signal, but there is some differences between input and output? I mean If I would like to register an input, I have to create the registerd signal like this:
I mean, it works, I can synthesize and simulate my project. However I saw something strange in the behavior of the other components instantiated. Maybe should I check better, but right now it is important to know that this part about the I/O synchronization is Ok.
Why not try simulating it all in modelsim. Without all of the code posted here I have no idea whats going on elsewhere. This code is very simple, and is unlikely to be causing any problems
adding registers should not affect the overall behaviour, unless you a relying on some sort of handshaking from an external source. I suggest you simulate your design.