How to refer the generated module?

[deathwaltz]

Hi~

I want to do a fast simulation by removing a complex module (CALC). Then I used generate statement like this below:
generate
if (fast_sim = = 1) begin
CALC u_calc(
);
end
endgenerate

However, I find that I can't refer the u_calc module in SIM_TOP which needs to defparam a parameter in u_calc module.
I have tried
u_fpga_top.u_calc.XXXX and
u_fpga_top.genblk1.u_calc.XXXX which according to modelsim generated signal name
Both will cause error Unresolved defparam reference to u_calc or genblk1.

So I want to ask, what the right format I should use. Or is there another way to get the job done.
Generate the module conditional
if the module is generated, defparam one parameter inside in SIM environment.

Thank you very much!:grin:

Ray

 

[dave_59]

You need to name generated blocks to refer to identifiers created in those blocks from outside the generated block.

if (fast_sim = = 1) begin :fast
     CALC u_calc(
);
end

The you can refer to u_fpga_top.fast.u_calc.XXXX


This is a requirement added by Verilog 1364-2005