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how to reduce transition time

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siva_7517

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hi,

How we can reduce the transition time in synthesis tools?

siva
 

In general the soluciont is to reduce capacitance, reduce resistence resistence or increse the current capability of the driver, this is don by:
Resize the source gate (increase the current capability, be careful with electromigration)
Redude fanout (reduce the capacitance)
Add buffers (reduce the capacitance/resistence, propagation delay is incremented)
Reduce de lenght of a line (resistance and capacitance is reduced)
Create a buffer tree. (reduce fanout, reduce capacitance and resistance, increase propagation dalea)
 

You can use some constraint setting in dc_shell.

set_max_transition
set_max_capacitance
set_max_fanout
 

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