How to reduce the ring and spike on VDS of MOSFET

[will_fung]

Hi,

I have an issue with the BOOST circuit. with the MOSFET of NVMFS5C670NL, there is no ring on the VDS (Low side MOSFET T53201 and T53202)). But when I change to NVMFS5C646NLAFT1G, the ring on VDS is observed. I also could observe the ring on Vgs.
Could you let me know why it happened? How to solve it?
Thank you.

NVMFS5C670NL datasheet:

https://www.onsemi.com/pdf/datasheet/nvmfs5c670nl-d.pdf

NVMFS5C646NLAFT1G datasheet:

https://www.onsemi.com/pdf/datasheet/nvmfs5c646nl-d.pdf

 

[cupoftea]

I suspect that the Cds is different and its resonating with some stray inductance somewhere in the cct.....does the ring happen when the hi side synchronous mosfet turns ON?
It could actually be common mode noise and nothing to worry about.....to check for this........attach the probe tip to the same node, but also attach the probe ground to that same node aswell.....if you still see the ringing, then it is just a "fake" ring.

How do you probe?...do you use scope probe with horrible inductive ground clip?...or do you use nice home-brew coaxial probe, and possibly with cable ferrite round it to get rid of the nasty common mode noise?
Do you have Thermal cam?...does it run much hotter (the one with the ring happening)?

 

[dick_freebird]

A low Cdg may be so high frequency that it escapes your vertical BW setting / capability.

A high Cdg might be dV/dt limited to the point that the resonant frequency at play, is higher than the edge-rate equivalent fundamental and it doesn't ring up.

Knowing that your test setup is only observing, and not meddling, is a key first layer of the onion.

 

[Rahul_d]

Since the NVMFS5C646NLAFT1G Ciss & Qgd is higher than older FET, try reducing your gate resistor from 6.8Ω to ~4.0Ω to 3.3Ω .

 

[will_fung]

I suspect that the Cds is different and its resonating with some stray inductance somewhere in the cct.....does the ring happen when the hi side synchronous mosfet turns ON?
It could actually be common mode noise and nothing to worry about.....to check for this........attach the probe tip to the same node, but also attach the probe ground to that same node aswell.....if you still see the ringing, then it is just a "fake" ring.

How do you probe?...do you use scope probe with horrible inductive ground clip?...or do you use nice home-brew coaxial probe, and possibly with cable ferrite round it to get rid of the nasty common mode noise?
Do you have Thermal cam?...does it run much hotter (the one with the ring happening)?

Hi,

No, the ring happens before the high side sync MOSFET turns on.
I'm using the shortest ground wire (the spring ground wire). I don't have a thermal camera, so I don't know the thermal dissipation. but I think I can measure the power efficiency later.
When i remove the 1.5nF capacitor on gate, the ring can be reduced, but the Vds overshoot is too high it may damage the controller.

 

[Easy peasy]

The signal on the Vd-s is getting into and affecting the Vg-s - due to the ratio of capacitances

To detune, several approaches may need to be applied, 1, rail snubbers on the DC bus, very near to the fets

2, a 1k resistor on the g-s

3, A small VHF bead ( SMT equivalent ) on the line to the gate - right by the gate - this has a high ohmic value at the VHF ringing frequency - and can very effectively limit the interaction from Vd-s to Vg-s removing pretty much all of the ringing ...

 

[cupoftea]

Easy Peasy's method sounds the Best way to do this.....but in the first instance, did you not try a simple signal diode to short out the gate series resistor going back to the controller at turn off?.....

Whats weird about your ringing is it happens fully after the low FET has gone through its turn off procedure.
You say it happens before the high fet turns on, but is it happening at the start of that turn on?

Have you tried to run it with no hi side fet and just a hi side schottky?...whats the ringing like then?

The classic fault for these sync boost converters is that when the hi side fet turns on, the low side fet gets spuriously turned on via the Cgd......thats solved by either slowing up the switch on of the hi side fet, or by, as youve done, adding the bit of low side gate capacitance.

And thats another point...have you tried slowing up the switch ON of the hi side fet.....i woudl recomend slowing up the switch on of the low side fet...but the ringing happens well after the switching off transition of the low side fet.