How to reduce the harmonic of current steering DAC?

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winsonpku

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dac harmonic

I have designed a 10bit 60MSPS current steering DAC.
The simulation showes the 3rd harmonic is a little large.
Simulation results are showed in attachment.
What is the reason of 3rd harmonic and how to reduce this?
Thanks!
 

in many paper i've read, it says that we have to increase the output impedance of current source..

i am in the middle of current-steering DAC design project too..
but i dont know how to simulate SFDR like you did..
could you u tell me how to do it?
and what did you do to simulate DNL and INL? because to me, it's very time consuming.. is there any alternative method to do that?
the simulator i'm using is SIMetrix.. what's your simulator?
 

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