How to reduce power consumption of MCML ?

[faizalism]

mcml in subthreshold

As we know, MCML draws static power which equal to, P=IV. As far as i know, static here is not mean on leakage and subthreshold. It refers to current source at the tail of the MCML. Let say I want to reduce the power consumption, I can simply change Vdd and current source. Or there is other effective ways/techniques to reduce it ?

request paper: M.Yamashina and H.Yamada, "An MOS current mode logic (MCML) circuit for low power-sub-GHz processor"

Thanks,

 

[tsb_nph]

Re: MCML static power

As we know, MCML draws static power which equal to, P=IV. As far as i know, static here is not mean on leakage and subthreshold. It refers to current source at the tail of the MCML. Let say I want to reduce the power consumption, I can simply change Vdd and current source. Or there is other effective ways/techniques to reduce it ?

request paper: M.Yamashina and H.Yamada, "An MOS current mode logic (MCML) circuit for low power-sub-GHz processor"

Thanks,

M.Yamashina and H.Yamada, "An MOS current mode logic (MCML) circuit for low power-sub-GHz processor"
this paper has been uploaded in this link :