how to reduce offset for the op-amp in a LDO?

[alicia8283]

how to reduce offset

i have an op-amp which is used for LDO. the Vref is about 1.16V.
At that point, my op-amp's offset is ~6mV will this a problem for my LDO?
How to lower the op-amp offset? my op-amp is only one stage op-amp which using high swing cascode current mirror as load current.
thanks in advance

 

[pfd001]

how to reduce offset of opamp

The opamp offset will affect the output voltage of your LDO. It depends on your specs whether 6mv is a problem.
To reduce the offset voltage, you can increase the channel length of your diffential pair

 

[JT]

reducing offsets in opamps

If this is a systematic offset, you should double check your design. Systematic offset in your opamp can be the effect of :
-low loop gain
-transistor that are biased in their triode region
-inequal W/L's in current mirrors and or differential pairs.

More important is to check whether your random offset is acceptable. If you have 6mV 6 sigma, this will be visible at the output of your LDO. (probably this is an amplified version of the reference voltage).

The random offset is defined by the matching of your input pair and your current mirrors, and this can be calculated when you have access to the process spec of your fab.

br, Jef

 

[vishnu438]

try increasing the length and width of the differntial pair and gm of the load and the diff pair has to be properly decied/