Can anyone tell me how to reduce interrupt latency of MSP430F1121.
Im using port interrupt and TIMERA0 (CCIFG i.e. CCR0=timer value) interrupt.
this is very urgen for me
thanks in advance
niks
im working at ACLK=MCLK=SMCLK=7.3728MHz.
Time delay betn Intr and first instruction of Intr body is around 13uS.
I think this delay is too much almost 100clks. 130uS is instruction cycle time.
Can someone tell me solution/clarification for same
Are you triggering the INT on the right edge ? It cannot take 100 clks to get from port pin change to start of INT routine - it looks like your INT is configured for rising edge while you are looking at Falling edge (or Vice versa!)
"The interrupt latency is 6 cycles, starting with the acceptance of an interrupt request, and lasting until the start of execution of the first instruction of the interrupt-service routine..." (slau049c.pdf)
HI
Im able to solve the problem. Actually problem is after PUC its setting OFIFG i.e. Osc Fault Intr Flag. previously i didnt checked it cuz normally we take care of that bit only in MSP430F149/135. But F1121 we need not take care. Now im just resetting flag .
i got expected result.
anyway thanks for the help and interest u showed in solving problem
regards
~niks~