yes I am using virtex ultrascale. as you mentioned the tool is spreading many blocks in multiple stacked silicon. But when I try to partition the design, specifying the pblock for critical blocks, the congestion on other modules increases. also because of all these congestion the routing time has increased to 14 hours.
The Lut utilization is 86 % and as the rtl is meant for Asic and its a complex architecture it has lot of asynchronous parts and loops which unfortunately I cannot change.
Thanks