How to reduce clk loads ( CLK load of 6255)?

[xtcx]

How to reduce clk loads?

Hi friends!,I'm using Xilinx ISE 10x ver and in my design I'm using a synchronous 40MHz CLK Input for my SPARTAN 3 CHIP. The INSTANCE name for clk input is CLK. When I saw the Clk report in PAR, it shows a CLK load of 6255. I don't well understand if this much load creates any problems like poor routing or clock speeds or poor performance!...My design just gives a poor clock timing of upto 38MHZ where as the expected clk freq is 40MHz....Is there anything I can deal with the clk load?.Or can I share the clk resources?...Please help me clear this doubt!....Thanks guys

 

[shitansh]

Re: How to reduce clk loads?

HI,

Try to pass your clock input from clock buffer and then use it.

It may help.

--
Shitansh Vaghela

 

[xtcx]

Re: How to reduce clk loads?

Could you be more specific?.Before using the clock in multiple process in my design, I shared the clock onto many local buffers(signals in this case.But there was no use in doing that. However I haven't tried using IC's Buffer resources such as "BUFG".Are you meaning the buffers like BUFG, BUFGMUX etc?....