Device size of course drives down mismatch.
You might first look at whether it's mismatch or process
(and/or temp) that accounts for base current difference.
Systematic design offsets can be highlighted at process
corners.
Degeneration helps when resistor variation matters less
(or is less, %-wise) than transistor variation.
Be sure the mismatch distribution that the MC setup
lays on you, is borne out by data. Modeling dudes
love to make stuff up and once the kit is done, have
zero motivation to go back and put real data in.
Make sure that bases see identical driving impedances,
this is where base current (hFE) mismatch turns into
voltage mismatch.