D.A.(Tony)Stewart
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YOu need two delay circuits. One to produce double edge clock using XOR (any period <<<50% of T is ok since only leading edge is used to reduce jitter) show below.
The Decoder latch uses a 2nd time delay that is leading edge trigger and non-retrigerable for the duration of 3/4 T where T is the symbol time to latch input data to decode correct phase of clock. Then this second clock is used to decode state of input to recover the data.
YOu can choose any Manchester protocol. Biø-M, Biø-S or Biø-I for mark, space or invert.
The Decoder latch uses a 2nd time delay that is leading edge trigger and non-retrigerable for the duration of 3/4 T where T is the symbol time to latch input data to decode correct phase of clock. Then this second clock is used to decode state of input to recover the data.
YOu can choose any Manchester protocol. Biø-M, Biø-S or Biø-I for mark, space or invert.