entity pwmedit is
PORT( clk100 : IN std_logic;
pwm_in : IN std_logic;
mult : IN integer:=1;
pwm_out: OUT std_logic);
end pwmedit;
architecture Behavioral of pwmedit is
signal cnt: integer:=0;
signal num_int: integer:=0;
process(clk100,pwm_in)
begin
if rising_edge(clk100)
then num_int <= num_int + 1;
if pwm_in ='1'
then num_int<=0;
cnt<=cnt+1;
else
if num_int < (cnt+784) * mult
then pwm_out <= '1';
else pwm_out <= '0'; cnt<=0;
end if; end if;
end if;
end process;
Dear All ,Thank you for suggestion, I spend two days to write it,because I am not good in vhdl and english,so this is working code:
View attachment 143875Code:entity pwmedit is PORT( clk100 : IN std_logic; pwm_in : IN std_logic; mult : IN integer:=1; pwm_out: OUT std_logic); end pwmedit; architecture Behavioral of pwmedit is signal cnt: integer:=0; signal num_int: integer:=0; process(clk100,pwm_in) begin if rising_edge(clk100) then num_int <= num_int + 1; if pwm_in ='1' then num_int<=0; cnt<=cnt+1; else if num_int < (cnt+784) * mult then pwm_out <= '1'; else pwm_out <= '0'; cnt<=0; end if; end if; end if; end process;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY pwm IS
GENERIC(
sys_clk : INTEGER := 1_000_000; --system clock frequency in Hz
pwm_freq : INTEGER := 60_000; --PWM switching frequency in Hz
bits_resolution : INTEGER := 8; --bits of resolution setting the duty cycle
phases : INTEGER := 1); --number of output pwms and phases
PORT(
clk : IN STD_LOGIC; --system clock
reset_n : IN STD_LOGIC; --asynchronous reset
ena : IN STD_LOGIC; --latches in new duty cycle
duty : IN STD_LOGIC_VECTOR(bits_resolution-1 DOWNTO 0); --duty cycle
pwm_out : OUT STD_LOGIC_VECTOR(phases-1 DOWNTO 0); --pwm outputs
pwm_n_out : OUT STD_LOGIC_VECTOR(phases-1 DOWNTO 0)); --pwm inverse outputs
END pwm;
ARCHITECTURE logic OF pwm IS
CONSTANT period : INTEGER := sys_clk/pwm_freq; --number of clocks in one pwm period
TYPE counters IS ARRAY (0 TO phases-1) OF INTEGER RANGE 0 TO period - 1; --data type for array of period counters
SIGNAL count : counters := (OTHERS => 0); --array of period counters
SIGNAL half_duty_new : INTEGER RANGE 0 TO period/2 := 0; --number of clocks in 1/2 duty cycle
TYPE half_duties IS ARRAY (0 TO phases-1) OF INTEGER RANGE 0 TO period/2; --data type for array of half duty values
SIGNAL half_duty : half_duties := (OTHERS => 0); --array of half duty values (for each phase)
BEGIN
PROCESS(clk, reset_n)
BEGIN
IF(reset_n = '0') THEN --asynchronous reset
count <= (OTHERS => 0); --clear counter
pwm_out <= (OTHERS => '0'); --clear pwm outputs
pwm_n_out <= (OTHERS => '0'); --clear pwm inverse outputs
ELSIF(clk'EVENT AND clk = '1') THEN --rising system clock edge
IF(ena = '1') THEN --latch in new duty cycle
half_duty_new <= conv_integer(duty)*period/(2**bits_resolution)/2; --determine clocks in 1/2 duty cycle
END IF;
FOR i IN 0 to phases-1 LOOP --create a counter for each phase
IF(count(0) = period - 1 - i*period/phases) THEN --end of period reached
count(i) <= 0; --reset counter
half_duty(i) <= half_duty_new; --set most recent duty cycle value
ELSE --end of period not reached
count(i) <= count(i) + 1; --increment counter
END IF;
END LOOP;
FOR i IN 0 to phases-1 LOOP --control outputs for each phase
IF(count(i) = half_duty(i)) THEN --phase's falling edge reached
pwm_out(i) <= '0'; --deassert the pwm output
pwm_n_out(i) <= '1'; --assert the pwm inverse output
ELSIF(count(i) = period - half_duty(i)) THEN --phase's rising edge reached
pwm_out(i) <= '1'; --assert the pwm output
pwm_n_out(i) <= '0'; --deassert the pwm inverse output
END IF;
END LOOP;
END IF;
END PROCESS;
END logic;
pls send me to XXXXXXXXXX, is there tachometer also used to correct some speed or hertz or rpm ??
There are no any fixed data needed, just it need to modify incoming pwm signal from flight controller and send it out to motor and regulate motor speed by getting hertz or revolution per 20ms .. So problem is solved , by myself and i want if someone need this he can use above code,because googling dont give me result..and no one write this kind of code.
So problem is solved , by myself and i want if someone need this he can use above code,because googling dont give me result..and no one write this kind of code.
entity pwmedit is
PORT( clk100 : IN std_logic;
pwm_in : IN std_logic;
mult : IN integer:=1;
pwm_out: OUT std_logic);
end pwmedit;
entity pwmedit is
generic ( mult : integer := 1); -- multiplayer
PORT( clk100 : IN std_logic;
pwm_in : IN std_logic;
pwm_out: OUT std_logic);
end pwmedit;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity pwmedit is
generic ( mult : integer := 1); -- multiplayer
PORT( clk100 : IN std_logic;
pwm_in : IN std_logic;
pwm_out: OUT std_logic);
end pwmedit;
architecture Behavioral of pwmedit is
signal cnt: integer :=0;
signal num_int: integer :=0;
begin
process(clk100,pwm_in)
begin
if rising_edge(clk100)
then
num_int <= num_int + 1;
if (pwm_in = '1')
then
num_int<=0;
cnt<=cnt+1;
else
if (num_int < ((cnt+784) * mult))
then pwm_out <= '1';
else pwm_out <= '0'; cnt<=0;
end if; end if;
end if;
end process;
end Behavioral;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY pwmedit_TB IS
END pwmedit_TB;
ARCHITECTURE behavior OF pwmedit_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT pwmedit
generic ( mult : integer := 1); -- multiplayer
PORT(
clk100 : IN std_logic;
pwm_in : IN std_logic;
pwm_out : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk100 : std_logic := '0';
signal pwm_in : std_logic := '0';
--Outputs
signal pwm_out : std_logic;
-- Clock period definitions
constant clk100_period : time := 100 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: pwmedit PORT MAP (
clk100 => clk100,
pwm_in => pwm_in,
pwm_out => pwm_out
);
-- Clock process definitions
clk100_process :process
begin
clk100 <= '0';
wait for clk100_period/2;
clk100 <= '1';
wait for clk100_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk100_period*10;
-- insert stimulus here
pwm_in <= '1';
wait for clk100_period*100;
pwm_in <= '0';
wait for clk100_period*100;
pwm_in <= '1';
wait for clk100_period*100;
pwm_in <= '0';
wait for clk100_period*100;
pwm_in <= '1';
wait for clk100_period*400;
pwm_in <= '0';
wait for clk100_period*400;
pwm_in <= '1';
wait for clk100_period*1000;
pwm_in <= '0';
wait for clk100_period*1000;
pwm_in <= '1';
wait for clk100_period*4000;
pwm_in <= '0';
wait for clk100_period*4000;
pwm_in <= '1';
wait for clk100_period*4000;
pwm_in <= '0';
wait for clk100_period*4000;
wait;
end process;
END;
entity pwmedit is
PORT( clk100 : IN std_logic;
pwm_in : IN std_logic;
mult : IN integer:=1;
pwm_out: OUT std_logic);
end pwmedit;
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