I can give you an principle SPI slave example. The shiftregister is operated from SPI clock. That isn't generally necessary, but gives a wider range of SPI clock speed in relation to FPGA/CPLD clock. As a disadvantage, synchronisation of data available event is necessary.
hi, my project is to interface PIC18F microcontroller with FPGA using SPI interface. the PIC microcontroller will act as a master and FPGA will be slave. can anybody help??? i dont know from where to start???
I see that besides a CIC decimation module you also have SPI on your shopping list. Two points .... First: check out the links provided by some_guy right above your post. And the second more sobering point ... implementing SPI is pretty trivial. Hell, it was one of the first things I wrote when learning verilog. Purely because it was easier than trying to figure out someone elses code back then. It really is easy, just try it. And the reason I suggest you try at least implement SPI yourself... If implementing something as easy as SPI is beyond your current skills (no prob, you can always learn), then it would be of no use to give you full working vhdl code for CIC decimation anyways. Why? Because you would have no clue how to integrate it into a working design, that's why.
So if you really want to learn VHDL, you might as well try to do the SPI yourself. After that look for useable VHDL for the other items on your shopping list and try and integrate that. Then come to the conclusion that well documented HDL is hard to come by, cave in, and code up the rest of the HDL yourself as well. And voila, you are suddenly well on your way to mastering the HDL of your choice. ;-)