Patrick Yang
Junior Member level 1
Hi all,
I am now working on a project that maybe use the hybrid architecture with 1st stage CT INT(Gm-C INT) and DT INTs for other stages. I don't have the experience of designing a CT DSM or a Hybrid one. There are some questions about this kind of architecture.
1, How to realize the CTINT from DT one, I set up a DT simulink model with 0.5/(z-1) for 1st INT, I don't know how to realize it by CT one. Is is correct to replace z = 1+sT, so 0.5/z-1 == 0.5*T/s, Although this approximation is reasonable in mathmatics, but how to realize it in cadence, how can we define the gain 0.5*T in CT integrator.
2, The input of 1st stage INT is the difference of signal input VIN minus feedback votlage VFB, normally, it would be equal to quantization noise 1/2^N VDD. But for a CT INT the OTA's gain is quite large, the quantization noise will definitely saturate the output of OTA. So how to deal with this problem.
Could anyone help answer my questions. Many thanks in advance.
Best,
I am now working on a project that maybe use the hybrid architecture with 1st stage CT INT(Gm-C INT) and DT INTs for other stages. I don't have the experience of designing a CT DSM or a Hybrid one. There are some questions about this kind of architecture.
1, How to realize the CTINT from DT one, I set up a DT simulink model with 0.5/(z-1) for 1st INT, I don't know how to realize it by CT one. Is is correct to replace z = 1+sT, so 0.5/z-1 == 0.5*T/s, Although this approximation is reasonable in mathmatics, but how to realize it in cadence, how can we define the gain 0.5*T in CT integrator.
2, The input of 1st stage INT is the difference of signal input VIN minus feedback votlage VFB, normally, it would be equal to quantization noise 1/2^N VDD. But for a CT INT the OTA's gain is quite large, the quantization noise will definitely saturate the output of OTA. So how to deal with this problem.
Could anyone help answer my questions. Many thanks in advance.
Best,