how to realize a 150db open loop gain OP in CMOS process

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eric.liu

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dear all
i want to design an OP with 150db open loop gain and 8MHz GBW with 220pF load, which architecture should I choose?
can a two stage OP with a gain-boosted cascoded stage as its first stage and a class AB stage as its second stage work? or choose a three stage OP architecture?
thanks!
 

Omm...

Are you designing TI's DRV603?
 

you need to put multiple stages. Depends upon process etc. If in trouble, try nested miller etc.
I have never done one of those. Just read.
 

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