BradtheRad,
Let's simply calculate, as pnp switch "on" in DT, "off" in (1-D)T,then when system is stable, (Iin-Iout)*DT=Iout(1-D)T--->IinD=Iout;
thus max of η=Pout/Pin=Vout*Iout/(Vin*IinD)=Vout/Vin; so just with this kind of SC capacitors ,we may couldn't get η>Vout/Vin; just as LvW conculated before; here also i confused how (vin-vout)/vin waste?
since switch with pwd of SC capacitors is not useful as η < LDO. maybe we only could use charge pump convertors.
So, my doubt become as follow:
1, if big extra capacitors outside is allowed, then how we can realize 2.5v-->1.2v while meeting ripple&η.
2, if use charge pump convertors, is the principles keep capacitors delta V constant(or means Q constant).and if it is,how can i realize vout adjustment as:1.0v,1.1v,1.2v.
At this point it's helpful to have diagrams showing the method which has been held up as the ideal. Theoretically this method is 100 percent efficient.
Stage 1 (The left-hand capacitors should be equal, so that they charge at the same rate):
Stage 2:
We can adjust duty cycle, switch rate, and capacitor values, in order to bring ripple within spec.
One thing not shown in the schematics is the impedance in the power supply. It has a lot to do with how fast the left-hand capacitors charge.
We have divided the supply by 2. But suppose net voltage to the load is slightly high? It can be reduced by putting a resistor or two somewhere in the loop. It will dissipate some power, reducing efficiency somewhat.
Suppose we want V/3? Then we stack 3 capacitors at the left. It will require adding more switches. (The switches are single-pole double-throw type.) No efficiency is lost. Using this process we can divide down to whatever level we wish.
Switches are inconvenient. To make a working project, we would like to replace all switches with mosfets. The hard part is figuring out how to do it yourself. It will require a lot of devices, because it takes 2 mosfets to do the job of 1 double-throw switch.
Furthermore each mosfet's gate voltage is referenced to the source terminal (n-mos) or drain terminal (p-mos). However the proper voltage may or may not be present at the proper terminal. Or it may not be sufficient. This brings in the likelihood that we need to step up voltages at gates, or use pulse transformers, etc.
What if we tried to use transistors? We would run into a similar problem. Bias currents would not necessarily have a clear path to ground (or to positive polarity in the case of PNP type). This stops transistors from operating properly.
So the project has become quite complex.
It's easier to use a simpler linear (voltage drop) step down configuration. Despite their wasting more power.
If an inductor is allowed, then greater efficiency is possible.