Here is my complete code...You can safely omit the statements corresponding to STATE = s0.Si9nce these are only codec initialization steps
Only statements from STATE <= S1 sequence are needed...My explanations at the end of this code...
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-------------------- ENTITY DECLARATION -------------------------
entity SDR_PSK is
PORT (
clk : IN STD_LOGIC;
sclk : in std_logic;
sw2 : IN STD_LOGIC;
sdofs : in std_logic;
sdo : in std_logic;
rst : out std_logic;
se : inout std_logic;
sdi : out std_logic;
sdifs : out std_logic;
---------
LED : OUT STD_LOGIC_VECTOR(15 DOWNTO 0):=x"0000";
-- clk_sdata_op : OUT STD_LOGIC;
-- clk_data_op : OUT STD_LOGIC;
-- ----------
Txb : OUT STD_LOGIC;
-- Rxb : OUT STD_LOGIC;
INT_OP : OUT STD_LOGIC;
TEST_OP : OUT STD_LOGIC
-- sdofs_op : OUT STD_LOGIC
);
end SDR_PSK;
------------------------ SIGNALS DECLARATION --------------------------------------
architecture Behavioral of SDR_PSK is
-----------CODEC-------------
TYPE main is (s0, s1);
SIGNAL state : main;
TYPE INTERRUPTS1 IS (NONE,SYNC_ON,SYNC_OFF);
SIGNAL INTERRUPT : INTERRUPTS1:= NONE;
--SIGNAL INTERRUPT : INTEGER :=0;
SIGNAL sig : INTEGER RANGE 0 TO 188 :=1;
SIGNAL sig1,t : INTEGER RANGE 0 TO 150 :=0; -- Must start with 0
signal Rx_buff1,Rx_buff2 : std_logic_vector(15 downto 0):="0000000000000000";
signal Tx_buff1,Tx_buff2 : STD_LOGIC_VECTOR(15 downto 0):="0000000000000000";
signal Tx1,Tx2,Tx : STD_LOGIC_VECTOR(31 DOWNTO 0);
signal Rx1,Rx2,Rx : STD_LOGIC_VECTOR(31 DOWNTO 0):=x"00000000";
signal enab : std_logic:='0';
constant ca1 : std_logic_vector(15 downto 0) := x"8901";
constant ca2 : std_logic_vector(15 downto 0) := x"8101";
constant ca3 : std_logic_vector(15 downto 0) := x"8a7b";
--------MARKER----------
----SIGNAL MARKER1 : STD_LOGIC_VECTOR(31 DOWNTO 0):="01111110011111100111111001111110";
SIGNAL MARKER1 : STD_LOGIC_VECTOR(15 DOWNTO 0):="0111111001111110";
SIGNAL DATA_Tx,DATA_Rx : STD_LOGIC;
SIGNAL TEST_REG : STD_LOGIC_VECTOR(31 DOWNTO 0):=x"AAAAAAAA";
----SIGNAL BUFFER_Tx : STD_LOGIC_VECTOR(47 DOWNTO 0);
SIGNAL BUFFER_MARKER,dummy : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL FLAG_RAMSWAP : STD_LOGIC:='0';
SIGNAL BUFFER_Tx,BUFFER_Rx : STD_LOGIC_VECTOR(31 DOWNTO 0);
--
--------------CODING-----------
SIGNAL CLK_RECOV_PRE : STD_LOGIC;
SIGNAL Mnchr_Rx,Mnchr_Tx,MONOSHOT_inv : STD_LOGIC;
SIGNAL Mnchr_Rx_inv,Mnchr_Rx_delay : STD_LOGIC;
SIGNAl CLK_RECOV,CLK_RECOV_inv : STD_LOGIC;
SIGNAL A,B,C,D,E,F,G,H,X : STD_LOGIC;
SIGNAL A1,B1,C1,D1,E1,F1 : STD_LOGIC;
SIGNAL MONOSHOT : STD_LOGIC;
SIGNAL m,n,o,m1,n1 : INTEGER:=0;
SIGNAl clk_data,clk_sdata : STD_LOGIC;
--
----------------------- PREDEFINED ASSIGNEMENTS ----------------------------------------------------
BEGIN
-----CODING AND MARKER---
--Txb <= DATA_Tx;
--Rxb <= DATA_Rx;
--clk_sdata_op <= clk_sdata;
--clk_data_op <= clk_data;
DATA_Rx <= DATA_Tx;
------------------------------------------------------------------------------------------------------------------------
-- 1. C O D E C I N T E R F A C E M O D U L E
-----------------------------------------------------------------------------------------------------------------------
process(clk,sclk,state,sw2,sdofs,se,enab)
VARIABLE i,i1 : INTEGER:=0;
VARIABLE j : iNTEGER := 0;
VARIABLE temp,temp2 : STD_LOGIC:='0';
begin
----------------------------------------------------------------------------------------------------------------
IF(sw2 = '0') THEN
sig <= 0;
state <= s0;
sig1 <= 0;
IF(enab = '0') THEN
se <= '0';
rst <= '0';
enab <= '1';
ELSIF(enab = '1') THEN
se <= '1';
rst <= '1';
enab <= '1';
end if;
ELSIF rising_edge(sclk) then
enab <= '0'; -- Allow the loop to pass next time
-----------------------------------------------
-- CONTROL WORD CONFIGURATION
-----------------------------------------------
-----------------------------------------------
-- Control Word 1
-----------------------------------------------
case state is
when s0 =>
sig <= sig + 1;
case sig is
when 1 => sdifs <= '1';
when 2 => sdifs <= '0';
sdi <= ca1(15);
when 3 => sdi <= ca1(14);
when 4 => sdi <= ca1(13);
when 5 => sdi <= ca1(12);
when 6 => sdi <= ca1(11);
when 7 => sdi <= ca1(10);
when 8 => sdi <= ca1(9);
when 9 => sdi <= ca1(8);
when 10 => sdi <= ca1(7);
when 11 => sdi <= ca1(6);
when 12 => sdi <= ca1(5);
when 13 => sdi <= ca1(4);
when 14 => sdi <= ca1(3);
when 15 => sdi <= ca1(2);
when 16 => sdi <= ca1(1);
when 17 => sdi <= ca1(0);
--------------------------------------------
-- Control Word 2
--------------------------------------------
when 18 => sdifs <= '1';
when 19 => sdifs <= '0';
sdi <= ca2(15);
when 20 => sdi <= ca2(14);
when 21 => sdi <= ca2(13);
when 22 => sdi <= ca2(12);
when 23 => sdi <= ca2(11);
when 24 => sdi <= ca2(10);
when 25 => sdi <= ca2(9);
when 26 => sdi <= ca2(8);
when 27 => sdi <= ca2(7);
when 28 => sdi <= ca2(6);
when 29 => sdi <= ca2(5);
when 30 => sdi <= ca2(4);
when 31 => sdi <= ca2(3);
when 32 => sdi <= ca2(2);
when 33 => sdi <= ca2(1);
when 34 => sdi <= ca2(0);
----------------------------------------------
-- Control Word 3
-----------------------------------------------
when 35 => sdifs <= '1'; -- CONTROL REGISTER C
when 36 => sdifs <= '0';
sdi <= ca3(15);
when 37 => sdi <= ca3(14);
when 38 => sdi <= ca3(13);
when 39 => sdi <= ca3(12);
when 40 => sdi <= ca3(11);
when 41 => sdi <= ca3(10);
when 42 => sdi <= ca3(9);
when 43 => sdi <= ca3(8);
when 44 => sdi <= ca3(7);
when 45 => sdi <= ca3(6);
when 46 => sdi <= ca3(5);
when 47 => sdi <= ca3(4);
when 48 => sdi <= ca3(3);
when 49 => sdi <= ca3(2);
when 50 => sdi <= ca3(1);
when 51 => sdi <= ca3(0);
state <= s1;
sig1 <= 0;
when others =>
end case;
-------CODEC INITIALIZATION PROCESS COMPLETES --------------------------------------------
-------------------------------------------------
-- DATA BUFFER IN & OUT ( This is a forever loop)
-------------------------------------------------
WHEN s1 =>
sdifs <= sdofs;
sig1 <= sig1 + 1;
case sig1 is
WHEN 0 =>
IF(sdofs = '1') THEN
sig1 <= 1;
ELSIF(sdofs = '0') THEN
sig1 <= 0;
END IF;
WHEN 1 => sdi <= Tx_buff1(15);
Rx_buff1(15) <= sdo;
INTERRUPT <= SYNC_ON;
WHEN 2 => sdi <= Tx_buff1(14);
Rx_buff1(14) <= sdo;
WHEN 3 => sdi <= Tx_buff1(13);
Rx_buff1(13) <= sdo;
WHEN 4 => sdi <= Tx_buff1(12);
Rx_buff1(12) <= sdo;
WHEN 5 => sdi <= Tx_buff1(11);
Rx_buff1(11) <= sdo;
WHEN 6 => sdi <= Tx_buff1(10);
Rx_buff1(10) <= sdo;
WHEN 7 => sdi <= Tx_buff1(9);
Rx_buff1(9) <= sdo;
WHEN 8 => sdi <= Tx_buff1(8);
Rx_buff1(8) <= sdo;
WHEN 9 => sdi <= Tx_buff1(7);
Rx_buff1(7) <= sdo;
WHEN 10 => sdi <= Tx_buff1(6);
Rx_buff1(6) <= sdo;
WHEN 11 => sdi <= Tx_buff1(5);
Rx_buff1(5) <= sdo;
WHEN 12 => sdi <= Tx_buff1(4);
Rx_buff1(4) <= sdo;
WHEN 13 => sdi <= Tx_buff1(3);
Rx_buff1(3) <= sdo;
WHEN 14 => sdi <= Tx_buff1(2);
Rx_buff1(2) <= sdo;
WHEN 15 => sdi <= Tx_buff1(1);
Rx_buff1(1) <= sdo;
WHEN 16 => sdi <= Tx_buff1(0);
Rx_buff1(0) <= sdo;
WHEN 17 => sdi <= Tx_buff2(15);
Rx_buff2(15) <= sdo;
WHEN 18 => sdi <= Tx_buff2(14);
Rx_buff2(14) <= sdo;
WHEN 19 => sdi <= Tx_buff2(13);
Rx_buff2(13) <= sdo;
WHEN 20 => sdi <= Tx_buff2(12);
Rx_buff2(12) <= sdo;
WHEN 21 => sdi <= Tx_buff2(11);
Rx_buff2(11) <= sdo;
WHEN 22 => sdi <= Tx_buff2(10);
Rx_buff2(10) <= sdo;
WHEN 23 => sdi <= Tx_buff2(9);
Rx_buff2(9) <= sdo;
WHEN 24 => sdi <= Tx_buff2(8);
Rx_buff2(8) <= sdo;
WHEN 25 => sdi <= Tx_buff2(7);
Rx_buff2(7) <= sdo;
WHEN 26 => sdi <= Tx_buff2(6);
Rx_buff2(6) <= sdo;
WHEN 27 => sdi <= Tx_buff2(5);
Rx_buff2(5) <= sdo;
WHEN 28 => sdi <= Tx_buff2(4);
Rx_buff2(4) <= sdo;
WHEN 29 => sdi <= Tx_buff2(3);
Rx_buff2(3) <= sdo;
WHEN 30 => sdi <= Tx_buff2(2);
Rx_buff2(2) <= sdo;
WHEN 31 => sdi <= Tx_buff2(1);
Rx_buff2(1) <= sdo;
WHEN 32 => sdi <= Tx_buff2(0);
Rx_buff2(0) <= sdo;
WHEN 33 =>
Tx_buff1 <= Rx(31 DOWNTO 16);
Tx_buff2 <= Rx(15 DOWNTO 0);
Tx(31 DOWNTO 16) <= Rx_buff1;
Tx(15 DOWNTO 0) <= Rx_buff2;
led <= Tx_buff1;
WHEN 100 => INTERRUPT <= SYNC_OFF;
WHEN 126 => sig1 <= 0;
WHEN OTHERS => NULL;
END CASE;
when others =>
end case;
end if;
END PROCESS;
-----------------------------------------------------------------------------------------------------------------------------
-------- 2. M A R K E R A N D B I T S T U F F I N G
-----------------------------------------------------------------------------------------------------------------------------
PROCESS(clk_sdata,clk_data,clk,sclk) IS
VARIABLE i,i1 : INTEGER:=0;
VARIABLE temp,temp2 : STD_LOGIC:='0';
VARIABLE FLAG_LOOP : STD_LOGIC:='1';
BEGIN
---------------------------------
---- CODEC CLOCK GENERATOR @1MHz
---------------------------------
IF RISING_EDGE(clk) THEN
i1:= i1+1;
IF (i1 = 40) THEN
temp2 := NOT(temp2);
clk_data <= temp2;
i1:= 0;
END IF;
END IF;
---------------------------------
CASE INTERRUPT IS
WHEN SYNC_ON =>
C: IF RISING_EDGE(clk_data) THEN
-- IF(INTERRUPT = SYNC_ON) THEN
INT_OP <= '1';
m1<=m1+1;
n1<=n1+1;
IF(m1>=0 AND m1<=30) THEN
Data_Tx <= Tx(m1); --convertuing Buffer data to serial
Rx <= Data_Rx(m1);
ELSIF(m1=31) THEN
Data_Tx <= Tx(m1); --convertuing Buffer data to serial
Rx <= Data_Rx(m1);
END IF;
-- ELSIF(INTERRUPT = SYNC_OFF) THEN
WHEN SYNC_OFF =>
m1 <= 0;
INT_OP <= '0';
WHEN OTHERS => NULL;
END CASE;
END IF;
-- END IF;
END PROCESS;
End Behavioral;
---------------------------------------------------------------------------------------------------------
While the COdec loop of STATE = S1 is a forever loop, which collects data from SDO (as well as writes data to SDI)and stores it temporarily in Rx_buff1&Rx_buffer2(Lch&Rxh),Tx_buff1&Tx_buff2 resp.Totally 32 bits. At the count of 33(sig1) I will pass this temp buffer Rx_buff1&2 to Tx and Tx_buff1&2 to Rx. So Rx and Tx are 32-bit buffer each which holds codec data.(Tx is read data from codec whereas Rx is the data to be written to codec).Any operations that have been done so far are only done under CODEC's SCLK. ALL CODEC read\write operations have been coded under "rising_edge(sclk)",where the SCLK is generated by the codec itself asynchronouly at 2MHz. So all operations execute at 2MHz. Now I need to read\write data from Tx and Rx resp using a 1MHz clk to get 1mbps data rate.That is I need to convert 2mbps data to a constant 1mbps rate....For 1MHz I generated it from my 80MHz FPGA master clk input which is under "Marker and Bit stuffing".Now here comes the problem...The data which we read from FPGA's 1MHz clk is not in phase or exactly the same with sclk. I checked it by dividing 1MHz from SCLK(codec clk) and cross-checked and compared with my FPGA generated 1MHz clk. Both are not same at all..It appears like the codec clk is not 1MHz but some 999.1MHz..As a result,I can see my FPGA 1MHz clk shifting faster than Sclk@1MHz in CRO clearly...Here the term "interrupt" is to generate a flag exaclty at the time when codec read\write starts...So I place my data at the same time inorder to avoid data-missing..The overseen view here is that I must quickly place my data within Interrupt = SYNC_ON.....Well if you have any doubts related,just ask....Thanks for your interests!.....