how to read this code

[amnakhan786]

Hi,
I am a beginner in vhdl, struggling with vhdl programming. I am currently reading books and trying to understand code by other authors. i have to understand a code structure like this:

entity declaration

architecture behavioral of entity is

signal declarations:

signal(0) <= '1' when signal_1(0)='0' and signal_2(0)='1' else '0';
signal(1) <= '1' when signal_1(1)='0' and signal_2(1)='1' else '0';
signal(2) <= '1' when signal_1(2)='0' and signal_2(2)='1' else '0';
signal(3) <= '1' when signal_1(3)='0' and signal_2(3)='1' else '0';

inport <=  data_in and not signal;

signal_4(0) <= '1' when signal(0)='0' and signal_2(0)='1' else '0';
signal_4(1) <= '1' when signal(1)='0' and signal_2(1)='1' else '0';
signal_4(2) <= '1' when signal(2)='0' and signal_2(2)='1' else '0';
signal_4(3) <= '1' when signal(3)='0' and signal_2(3)='1' else '0';

inport_1 <= signal or signal_4;

process(clk)
do something here
.
.
end  process

end behavioral

my question is:

1)how this code will work, for behavioral part all statements execute concurrently, but signal_4 depends on signal so will second when-else would wait for signal computation?
2) how inport would be computed, concurrently or sequentially?
3)are all when else for signal computed simultaneously?
4)if i want to count how many bits of signal are turning to '1' after all 4 bits are computed is the 1's counter after when else for signal is the only way to do it? can i somehow count 1's within the when else?
5) if i want the same number of bits to go high for signal and signal_4, how can i do it?

I appreciate any help.
thanks

 

[TrickyDicky]

1. It wont wait, it will just use the current version of "signal". so as signal updates, signal_4 will update.
You need to understand how HDL simulation works. Signal assignments cannot really occur instantaneously, so simulation has a concept of deltas, which are an infinitely small amount of time. Signals are scheduled to update a minimum of 1 delta (you can specify an actual time with an after statement - but remember this is just for simulation) when a signal on the RHS of the assignement (or a signal in a process sensitivity list) changes.

But remember this is just simulation. On real hardware all of these signal assignments will equate to wires and gates. So in theory there is no delay between assignments, which is simulated using the delta system.

2. concurrently (see above)
3. yes
4. You can use arithmetic functions like +, -, * if you use the correct packages. But you need to understand what logic will be produced.
5. I guess thats your assignment. Think about how you would do it with digital logic, not with VHDL. VHDL is a description language after all, not a programming language. If you dont know what the circuit should be, you cannot expect to describe it with VHDL.

 

[amnakhan786]

thanks for the reply, i wanted to mention in my post that its not homework but i have somebodys code and i want to change it to incorporate my needs, i work with C++ mostly so vhdl is new for me. its part of my project. I know very little vhdl, so i am reading the available code and modifying at the same time.

 

[TrickyDicky]

I would highy suggest you stop right now. As a C++ guy, and no VHDL or hardware knowledge, you are liable to make a mess of it.
I suggest you find out what the circuit does first, and make a diagram of it. Then modify the diagram, and only then write the VHDL code mods. VHDL is a hardware description language, not a programming language. If you dont know what the hardware should be, then you shouldnt be writing the VHDL.