lgdly
Newbie level 3
Lets say that the top level contains module X.
Module X has inputs A, B of std_logic_vector and outputs of C and D (also std_logic_vector).
Module X contains within its architecture (using component/direct instantiation) Module Y.
Module Y has inputs M, N of std_logic_vector and outputs E, F (also std_logic_vector).
How can I write my VHDL to describe:
The output of Module X (C for example) is the input M to module Y.
ie. Module X could be a FSM, which outputs an enable signal (C), and this is connected to input M of module Y.
When this is high, module Y can now perform its role (a counter for example, with input M being an enable).
In addition the output E of module Y is wired up to be the output of D of Module X
I currently get the error that Xilinx cannot read from an output and I should use inout/buffer, but this doesn't seem to work. If this question is too abstract I will update it with code and the error messages along with a schematic.
Module X has inputs A, B of std_logic_vector and outputs of C and D (also std_logic_vector).
Module X contains within its architecture (using component/direct instantiation) Module Y.
Module Y has inputs M, N of std_logic_vector and outputs E, F (also std_logic_vector).
How can I write my VHDL to describe:
The output of Module X (C for example) is the input M to module Y.
ie. Module X could be a FSM, which outputs an enable signal (C), and this is connected to input M of module Y.
When this is high, module Y can now perform its role (a counter for example, with input M being an enable).
In addition the output E of module Y is wired up to be the output of D of Module X
I currently get the error that Xilinx cannot read from an output and I should use inout/buffer, but this doesn't seem to work. If this question is too abstract I will update it with code and the error messages along with a schematic.