How to read the output of a module in VHDL (Xilinx) and use this as input?

[lgdly]

Lets say that the top level contains module X.

Module X has inputs A, B of std_logic_vector and outputs of C and D (also std_logic_vector).

Module X contains within its architecture (using component/direct instantiation) Module Y.

Module Y has inputs M, N of std_logic_vector and outputs E, F (also std_logic_vector).


How can I write my VHDL to describe:

The output of Module X (C for example) is the input M to module Y.

ie. Module X could be a FSM, which outputs an enable signal (C), and this is connected to input M of module Y.

When this is high, module Y can now perform its role (a counter for example, with input M being an enable).

In addition the output E of module Y is wired up to be the output of D of Module X


I currently get the error that Xilinx cannot read from an output and I should use inout/buffer, but this doesn't seem to work. If this question is too abstract I will update it with code and the error messages along with a schematic.

 

[ads-ee]

a. Use VHDL 2008 which allows reading of an entity's output port
b. Create a c_local signal and use that as the local output then assign it to c for the entity's output.

 

[lgdly]

Is there any way around point a without using VHDL 2008?

Do you mind expanding point b please? I'm new to VHDL. Thanks

ie creating a c_local signal, is this an internal signal inside module X which is then assigned to module X output?

 

[shaiko]

d. Declare the output port as "buffer". (Although IMO it's the least preferable option...)

 

[TrickyDicky]

Is there any way around point a without using VHDL 2008?

Do you mind expanding point b please? I'm new to VHDL. Thanks

ie creating a c_local signal, is this an internal signal inside module X which is then assigned to module X output?

Like this - create a local internal copy of the output :

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Code VHDL - [expand]
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signal op_i : std_logic_vector(7 downto 0);
 
.....
 
process(clk, reset)
begin
  if reset = '1' then
  elsif rising_edge(clk) then
    op_i <= some_ip;
 
    if op_i = x"AB" then
      --do something based on output
   end if;
  end if;
end process;
 
op <= op_i;    -- connect output to local internal copy of output.

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