thanks, if I understand correctly, you mean this line (data <= to_slv(resize(scale*to_sfixed(in, 0, -11), 7, -6))
here, I still resize it to 14 bit because I did extend the sign extension in C code, meaning the input to the C code is still 14 bits.
I also tried with another approach where I use (data <= to_slv(resize(scale*to_sfixed(in, 0, -11), 9, -6))
and to get the data of 16 bits directly fed to Nios. I got the same issue.
The required sign extension to 16-bit can be performed by the resize() function. But you are doing it wrong because you are resizing to a vector with 14 bit length.
For the other points, you should provide a complete code example instead of two-line snippets which are lacking of most essential information.
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Ok, I thought I should make it simpler:
From vhdl, the data is the input to Nios.
Code:
data <= to_slv(resize(scale*to_sfixed(in, 0, -11), 9, -6));
"scale" is any number to represent the peak value, "in" is a sinusoidal waveform. "data" is the input to the Nios II.
In the C code, initially, I read the data from vhdl block using the C code below:
Code:
alt_16 data=0;
data = IORD_ALTERA_AVALON_PIO_DATA(data_base);
After this, the Nios system do some calculation (multiply with "a" for instance, where a is not a constant depending on calculation on some other inputs) to give a new value of "data", say name it as "data_new".
After the calculation, I want to assign "data_new" back to another custom block in vhdl say "block b".
Finally, I write the "data_new" back to another custom block in vhdl say "block b".
Code:
IOWR_ALTERA_AVALON_PIO_DATA(data_new_base, data_new);
I am not getting the correct value of "data_new" fed to the fpga, what could be the causes? timing issue? clock? What aspects can I look into?