Prasanna hegde
Newbie level 3
Hi,
How to scan the rotary switch using verilog. I'm new to verilog and FPGA, I've to look for the rotary switch movement and have to increment the data. when i turn the rotary switch it makes FPGA pins to get contact with GND. So in the user guide it has mentioned that we need to pullup the FPGA pin which is connected to rotary switch then when we turn it, that pin goes low. I did understand the concept but how to put it in the code.
I tried to watch the lavel of this pin using always @ (negedge rot)
but i was getting error while routing process. I think it's considering this net as clock. the error msg is ....
ERROR
lace:1018 - A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB / clock site pair. The clock component <rot_BUFGP/BUFG> is placed at site <BUFGMUX_X2Y0>. The IO component <rot> is placed at site <R14>. This will not allow the use of the fast path between the IO and the Clock buffer. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING and
allow your design to continue. However, the use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. A list of all the COMP.PINs used in this clock placement rule is listed below. These examples can be used directly in the .ucf file to override this clock rule. < NET "rot" CLOCK_DEDICATED_ROUTE = FALSE; >
please help
Thanks n regards,
Prasanna
How to scan the rotary switch using verilog. I'm new to verilog and FPGA, I've to look for the rotary switch movement and have to increment the data. when i turn the rotary switch it makes FPGA pins to get contact with GND. So in the user guide it has mentioned that we need to pullup the FPGA pin which is connected to rotary switch then when we turn it, that pin goes low. I did understand the concept but how to put it in the code.
I tried to watch the lavel of this pin using always @ (negedge rot)
but i was getting error while routing process. I think it's considering this net as clock. the error msg is ....
ERROR
lace:1018 - A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB / clock site pair. The clock component <rot_BUFGP/BUFG> is placed at site <BUFGMUX_X2Y0>. The IO component <rot> is placed at site <R14>. This will not allow the use of the fast path between the IO and the Clock buffer. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a WARNING andallow your design to continue. However, the use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. A list of all the COMP.PINs used in this clock placement rule is listed below. These examples can be used directly in the .ucf file to override this clock rule. < NET "rot" CLOCK_DEDICATED_ROUTE = FALSE; >
please help
Thanks n regards,
Prasanna
