Unfortunately you have hit a brick wall then and I can be of little help if init_calib_complete is LOW.
1. Check if you are supplying the proper clock and reset signals to the core. Check in simulation in any of your signals are going 'X'.
2. Compare your design with MIG DDR3 example design and observe the differences.
3. Other than following the debug methodologies given in the Xilinx MIG core spec, you may post your problem with the details in the Xilinx forums. Use the ILA and VIO debug cores to the best.