How to provide clock skew in VHDL ??

[Avii13]

I have written a VHDL code for PRBS. Its working fine.
Now i want to add clock skew to know the threshold value of delay after which PRBS will not work. Say clock reach at FF1 at T time and the same clock reach at FF2 at T+t1 time.
I used

process
begin
WAIT FOR 20ps ;
if clk'event and clk = '1' then

q <= d ;
end if;
end process ;

but its not working
How can I add this "t1" delay in clock in VHDL.?? Please sugeest

 

[AdvaRes]

You have to use 2 clocks in that case.

 

[Avii13]

You have to use 2 clocks in that case.

Can't it be done using same clock ??