Re: VHDL Code Protection
this or NGC files. NGC files are the synthesis output as a netlist -- before mapping/placement/routing. This works best when there are little or no extra timing/placement constraints for the core. At this point, the end user won't have the VHDL/Verilog. You would need to look up instruction on how to make an NGC of a specific portion of your design, making sure to handle IOB's correctly.
Popular IP cores often include code that will disable the core after some period of time has elapsed. for basic methods, it would still be possible to use FPGA editor to work around the protection without too much difficulty.