al_extreme
Member level 4
buffer
Im looking for a methode to protect ioport of my FPGA. My io run at 100 mhz and I need a dip or plcc pakage. I need current and voltage protection. Thanks for your help
Im looking for a methode to protect ioport of my FPGA. My io run at 100 mhz and I need a dip or plcc pakage. I need current and voltage protection. Thanks for your help