How to protect the I/O port of my FPGA ?

[al_extreme]

buffer

Im looking for a methode to protect ioport of my FPGA. My io run at 100 mhz and I need a dip or plcc pakage. I need current and voltage protection. Thanks for your help

 

[ashishjindal76]

buffer

hi

ur question is not clear. y u want to protect ur port. which application requires protection n for what purpose u need dip or plcc package


bye
ashish

 

[tlp71@hotmail.com]

Re: buffer

what do you mean?

to work at 100 mhz you need a latest fpga devices, many of this are 3.3V only and not 5 v tolerants, whic voltage you would use?
If you insert a buffer you must use a very fast device otherwise you cut your frequency

 

[al_extreme]

Re: buffer

Sorry for my poor english. I curruently working on a Logic analyser for student, I want to protect the input, exemple if the student made a bad connection the buffer will broke not the fpga. For that reason I want a easy package to remove and put another one easely. I using a spartan 2e fpga thank you very mutch for your help !

 

[tom_hanks]

Re: buffer

hiya,
u knw IO protection is always problem..
i guess fpga n internal logic will not solve the problem..

may be u need to make special PCB for this..
Take all major pins on test points..
and write clearly that its in Input pin or Output pin..
and if possible give the pin number also with that..

coz its headach otherwise to count pins again n again..

tom

 

[moira]

buffer

u mean,u just want to make sure which package of FPGA u should choose, don't u?
or to design a protect ciucuit?

if package of FPGA, i suggest PLCC, well, u could use a chip carrie socket for PLCC.
in my design ,i use CPLD,EPM7128SLC84, for removing it expediently,i bought a PLCC socket.

and to design a demo board, i've used 4 headers for the io pins of CPLD,all io pins coludn't connect directly with their corresponding pins of other chips on the board.

 

[bibo1978]

Re: buffer

I am not quite sure what you are asking about so I will ask some question hopefully this may clarify and help us to help you.

Are you doing a PCB design ?
What kind of Lab you are using, and the kind of users?
Do you want to tolerate 5-V signaling on the IO of the SpartanIIE?
What is/will be the descrete components Voltage standards in your PCB ?
Can you use a BGA FPGA in your board?

regards

 

[al_extreme]

Re: buffer

Im doing a desing of a pcb with a Spartan 2e 208 pin. I am building a logique analyser at 100 mhz. This is done, but I'm looking for a way to protect the input.

Example if I make a mistake ant put a 12 volts on the input, I want a component to protect that. No mathers is this component broke at 12 volts, but I need a package on a socket to change it easily plcc or dip.

Thank you very mutch for your help

 

[Git]

Re: buffer

I have seen such things, but I can't remember where. You could make your own small PCB. chip on top, pins pointing out of the bottom in a pin grid array or something.


Git

 

[power-twq]

Re: buffer

you can connect a bus switch device (actually a resistor that can be open

or closed) between your fpga's IO ports and other device on the board.

best regards

Im looking for a methode to protect ioport of my FPGA. My io run at 100 mhz and I need a dip or plcc pakage. I need current and voltage protection. Thanks for your help