How to properly short together named nets for schematic and layout (Cadence Virtuoso)

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I'm trying to short together multiple named nets in a digital bus- previously when I was just testing on a schematic level, I used 0 ohm resistors from the analoglib library, but as I'm now working on layout (tsmc 65nm), this isn't an option. Is there a specific block or layer used to do this and avoid LVS errors, or is the best option just to use a very tiny resistor in between each net?

(http://imgur.com/a%2FHqaKIQH)
 

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A presistor will netlist as a short for LVS and a resistor for Spectre.
What it will do for a logic netlister, I do not know.

Way, way back (like Edge) we saw we could place a label on one
part of a net, and a different label on another segment if there
was a 90-degree bend in the "wire" on the schematic. I do not
know whether this behavior has persisted, or not. For example
I would rip a but with a tap (like D<13>) and then at another
point past such a "feature", call it something else like D13local.

Never seemed sensible, to have two names on a net, but it did
"work" (i.e. I could simulate, layout folks could get LVS to pass).

I prefer the presistor these days since now I do little with
digital, and I know exactly what I'm going to get.
 

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