How to properly do chip floor planning?

[quaternion]

I am newbie in the field of layout .I want to know how different parts of an analog system are arranged on the silicon area . If for example each part is assigned a certain area that is square this will waste silicon area & if each is assigned a fixed area that can be a rectangle so it will be hard to optimize area usage. And in both cases the system performance will be affected by the different positioning & dimensionality of different parts of the system. Who are the responsible for making such arrangements are they the analog designers of different parts?And How?

And I want to know what about the power management of different parts , for example how regulators could be arranged with the different parts of the system?

Please, clarify these to me, or recommend a good brief reference.

 

[layoutmaster]

Chip Floor planning

Just to avoid typing the same again and again, make a search on this same forum about Floorplanning, I remember at least 2 or 3 topics where I gave my comments and recommendations about Analog chips Floorplanning.

In addition, I would recommend you to read Alan Hastings book The Art of Analog Layout, it has some interesting Floorplanning information and, more if you're a newbie, this is a "must read"...

 

[quaternion]

Re: Chip Floor planning

I am sorry , i did a quick search & thought that most of the floor planning discussions were about digital floor planning .

After some search still this question remains.

for example how regulators could be arranged with the different parts of the system?

Specially if the regulators are supplying digital & analog blocks (noisy & noiseless blocks).