module sensor(sw0,clk,hex0,sdo,sdi,cs,sclk);
input sw0,clk;
output [7:0] hex0;
input sdo;
output cs,sdi,sclk;
reg cs,next_cs;
reg sclk_ctrl,next_sclk;
reg sdi,next_sdi;
reg [7:0] address;
reg [7:0] data,next_data;
reg [3:0] cnt,next_cnt;
reg [2:0] state,next_state;
pll p0(
.inclk0(clk),
.c0(clk2)
);
assign sclk=(sclk_ctrl)?clk2:1'b1;
assign hex0=(cs)?data:8'd255;
always @(negedge clk2) begin
if(sw0) begin
state<=next_state;
cs<=next_cs;
sclk_ctrl<=next_sclk;
cnt<=next_cnt;
end
else begin
state<=3'd0;
cs<=1'b1;
sclk_ctrl<=0;
cnt<=4'd15;
address<=8'b10000000;
end
end
always @(posedge clk2) begin
if (sw0) begin
sdi<=next_sdi;
data<=next_data;
end
else begin
sdi<=1'b0;
data<=8'd0;
end
end
always @(*) begin
case (state)
3'd0: begin
next_state=(sw0)?3'd1:3'd0;
next_cs=1'b0;
next_sclk=1'b0;
next_cnt=4'd15;
next_sdi=1'b0;
next_data=data;
end
3'd1: begin
next_state=3'd2;
next_cs=1'b0;
next_sclk=1'b1;
next_cnt=4'd15;
next_sdi=1'b0;
next_data=data;
end
3'd2: begin
next_state=(cnt==8)?3'd3:3'd2;
next_cs=1'b0;
next_sclk=1'b1;
next_cnt=cnt-8'd1;
next_sdi=address[cnt-8'd8];
next_data=data;
end
3'd3: begin
next_state=(cnt==0)?3'd4:3'd3;
next_cs=1'b0;
next_sclk=1'b1;
next_cnt=cnt-8'd1;
next_sdi=1'bx;
next_data={data[6:0],sdo};
end
3'd4: begin
next_state= 3'd5;
next_cs=1'b0;
next_sclk=1'b0;
next_cnt=cnt;
next_data=data;
end
3'd5: begin
next_state=(sw0)?3'd5:3'd0;
next_cs=1'b1;
next_sclk=1'b0;
next_cnt=cnt;
next_data=data;
end
default: begin
next_state=(sw0)?3'd1:3'd0;
next_cs=1'b1;
next_sclk=1'b0;
next_cnt=4'd15;
next_sdi=1'b0;
next_data=8'd0;
end
endcase
end
endmodule **broken link removed**