As I understand, there is no VGS stress, but VDS stress equivalent to the supply voltage has to be tolerated which is a problem. If you use a cascode device as you have indicated, the LDO wont really be low-drop-out out in addition to causing large area and low efficiency. Moreover the VDG stress is not reduced. You could use the bottom transistor as a switch and while turning it off, tie it's source to some intermediate value (VDD/2) between supply and ground to share the VDG and VSG stresses. RON of the switch transistor would add to the drop-out voltage though.