How to power off some array elements

[ssubha]

I need to selectively put the elements of array in high power mode. The rest of the elements in the array are put off i.e. no power supply is given to them. Is this achievable in electronics design?
For example: if i have the following verilog code
reg [0..3] arr[0..7];
i would like to have arr[0], arr[2] enabled and all other array elements disabled during operation. Is this possible?

Thank you,
s.subha

 

[kingslayer]

Dear ssubha,

supply voltage cut-off is possible; this is called power gating. However, from what you write, you need very fine grain power gating, and I don't know what are the drawbacks on this. However, you will not see power gating at RTL code, but during the backend of the flow, while inserting header/footer transistors to implement power gating.

Cheers

 

[ssubha]

I request you to let me know that When the array elements are put in power off, the data is retained in them