HOW TO PLOT W Vs CAPACITANCE CURVE IN CADENCE?

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abselgec

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hi,
i'm trying to plot the width dependent nature of input capacitance of a gate (eg. cmos inverter). Currently i'm finding it by parametric analysis and printing the dc operating point. For this i have to add all individual input Cgg. Is there any method to plot this in a graph??
 

under the calculator info tab you'll find all functions that can be used to plot OP and model parameters...
 

From the top menu of ADE L window choose Tools->Results Browser.There you can find what you want and plot the Cgg VS. W graph.
 

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