How to pipeline Loop Logic?

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davyzhu

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loop logic

Hi all,

It's intuitive to pipeline a feed-forward combinational logic. But how to pipeline the Loop without changing the timing?

For example, when I insert a reg to feed-forward logic, shall I delete a reg in feedback logic at the same time?

And if the datapath logic is a iteration one(Logic A -> Logic B -> Logic A -> Logic B ...)? How to do pipeline?

Any suggestions will be appreciated!

Best regards,
Davy
 

Is your logic DSP alogorithm related? If it is (for example,IIR filter) ,use clustered look-ahead , scattered look ahead method to translate the prototype algorithm to architecture.
Generally, loop logic is not easilly pipelined.
 

I don't think inserting reg in loop without changing timing can be achieve, unless you use new algorithms.
 

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