library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fsm is
port (
clk: in std_logic;
rst: in std_logic;
x: in std_logic;
y: in std_logic;
a: out std_logic;
b: out std_logic
);
end entity;
architecture behavior of fsm is
type state is (ONE,TWO,THREE);
signal s_current, s_next: state;
--internal signals used by state machine
signal a_sm: std_logic;
signal b_sm: std_logic;
begin
fsm_process: process (s_current, x, y)
begin
-- state machine default values and output
s_next <= s_current;
a_sm <= '0';
b_sm <= '0';
case s_current is
----------------------------- STATE ONE -----------------------------
when ONE =>
if x = '0' then
s_next <= ONE;
else
s_next <= TWO;
end if;
if y = '1' then
a_sm <= '1';
end if;
----------------------------- STATE TWO -----------------------------
when TWO =>
if x = '0' then
s_next <= TWO;
else
s_next <= THREE;
end if;
if y = '1' then
b_sm <= '1';
end if;
----------------------------- STATE THREE -----------------------------
when THREE =>
if x = '0' then
s_next <= THREE;
else
s_next <= ONE;
end if;
if y = '1' then
a_sm <= '1';
b_sm <= '1';
end if;
----------------------------- DEFAULT -----------------------------
when others =>
s_next <= ONE;
end case;
end process;
--init state machine register
fsm_reg: process(clk)
begin
if (clk'event and clk = '1') then
if (rst = '1') then
s_current <= ONE;
a <= '0';
b <= '0';
else
s_current <= s_next;
a <= a_sm;
b <= b_sm;
end if;
end if;
end process;
end architecture;