How to minimize power consumption for CMOS logic?

[vreddy]

minimize power

can anyone expain, for CMOS logic give the various techniques to minimize power consumtion.???

thanks in advance.....

 

[irfansyah]

Re: minimize power

One way is to lower the supply voltage, it gives quadratic power savings, ideally.

Sizing transistors also matters, for example of an inverter, it's suggested that the output transition slope is much longer than the input rise/fall time, to reduce static current dissipation. But again, if we look at the global picture, making them roughly the same is a reasonable approach.

 

[manu_leo]

Re: minimize power

use mtcmos