Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

How to minimize clock power in ASIC based designs

Status
Not open for further replies.
A

a_shirwaikar

Newbie level 6
Joined
Mar 1, 2011
Messages
11
Helped
1
Reputation
2
Reaction score
1
Trophy points
1,283
Activity points
1,376
hey,
does anyone have any good links or ideas on how to minimize clock power specifically in ASIC based designs?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top