How to measure the power of a signal?

[keerthna]

How do I measure the power of a signal i.e., the instantaneous power and also the voltage and current at any given instant of time? I have to do this in Verilog. Is there any piece of code that I can write?

 

[KlausST]

Hi,

Power P = U x I.
To measure intataneous power you need two ADC channels to measure U and I simultaneously.
How to control the ADC is given in their datasheet.
The mathematics U x I should not be the problem.

This result as a single value is not very informative on AC signals.
Here you might use averaging to get the working power.

You don't describe where you see the problem. You don't describe much.

So we don't know waveform, frequency, U range, I range, application, cos-phi, and so on.
Therefore we can't give you detailed assistance.

Klaus

 

[keerthna]

I wrote a verilog code to measure the frequency of a signal. Using two counters. And this is how my code looks.

---

Code Verilog - [expand]
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module scopemeasure(signalin,clk,q,rst,edgedet);
input clk;
input signalin;
input rst;
 
reg [24:0]count1;
reg [24:0]count2;
output edgedet;
reg edgedet;
output [3:0]q;
reg[3:0]q;
reg signald;
reg tempedge;
 
 
reg flag;
 
reg high;
 
initial
begin
 
 
count1=0;
count2=0;
flag=0;
end
 
always@(posedge clk)
begin
if(rst==1)
begin
signald<=1'b0;
count1=0;
tempedge<=signalin&(~signald); 
end
else
begin
count1=count1+1;
high=0;
signald<=signalin;
tempedge<=signalin&(~signald); 
end
 
 
if((count1>=25'b1111101111000101001000000)&&(count1<=25'b1111101111000101100001000))
 
 
begin
count1=0;
high=1;
flag=0;
end
 
 
 
if(tempedge==1)
begin
count2=count2+1;
edgedet<=tempedge;
end
if(high==1)
begin
q[0]=count2[0];  
 q[1]=count2[1];
 q[2]=count2[2];
 q[3]=count2[3];
 
 
count2=0;
end
end
 
endmodule

---

Now how do I measure the power of the signal?

 

[KlausST]

Hi,

Now how do I measure the power of the signal?

Did you read post#2?

Klaus

 

[ads-ee]

I recommend you learn the difference between blocking (=) and non-blocking (<=) assignments.

You are both mixing them in the same procedural always block and you are using blocking in a edge triggered always block.

Have you tried this in a simulator and synthesis tool? Looking over the code you're setting count1 in multiple places, which should end up as a multiple driver problem. You also have the same issue with some of your other signals.

 

[keerthna]

Yes I did read the post but i didnt get a clear picture of how do i do it using verilog?

I have simulated and synthesized the tool and my program works perfect. I just need to know the procedure to measure power.

 

[FvM]

I don't see how voltage and current is represented in your design. There should be digitized analog signals.

 

[hoanglongroyal]

hi friend,
I really think we need a Analog Mixed Signal here. digital design can't not catch any current/voltage to do the power calculation.