How to measure the duration of a pulse in VHDL

[Dijskstra]

I'm trying to measure a pulse duration and I wrote the code below.

I'm simulating the pulses by pressing one push button, so, the pulse durations are multiple of seconds (not miliseconds nor microseconds)

What I want is the following:

1 - When a press a button, the counter resets

2 - While I'm pressing the button, the counter (pulse duration) increments

3 - When I release the button the counter shows it's content (pulse duration) in a row of 7 leds.

I've tryed the following code: (I know this is a very naive code, but I'm a beginner)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity Pulse_Duration is
    Port ( clk,
           Button : in  std_logic;
           Led0,
           Led1,
           Led2,
           Led3,
           Led4,
           Led5,
           Led6,
           Led7 : out  std_logic
--        Display : out std_logic_vector(7 downto 0)
    );
end Pulse_Duration;

architecture Behavioral of Pulse_Duration is
    signal temp: std_logic_vector(7 downto 0);
begin
    process(clk, Button)  --   <---------------------- THIS IS 'line 31'
        constant DIVISOR : integer := 50000000;  -- 50 MHz clock => Xilinx Spartan 3e
        variable count   : integer range 0 to DIVISOR-1;  
    begin
        -- button pressed
        if rising_edge(Button) then  -- 'Button' is asynchronous from 'clk' and must have priority over 'clk'
            temp(0) <= '0';
            temp(1) <= '0';
            temp(2) <= '0';
            temp(3) <= '0';
            temp(4) <= '0';
            temp(5) <= '0';
            temp(6) <= '0';
            temp(7) <= '0';
        -- temp <= "00000000";
        else
            if rising_edge(clk) then
                if count=DIVISOR-1 then  -- see if counter == 49999999
                    count := 0;          -- reset counter
                    temp <= temp + 1;    -- increment pulse duration 
                else
                    count := count + 1;  -- increment counter
                end if;
            end if;
        end if;
    end process;


    
    process(Button)
    begin
        if falling_edge(Button) then  -- Button released, then pulse duration displayed
            Led0 <= temp(0);
            Led1 <= temp(1);
            Led2 <= temp(2);
            Led3 <= temp(3);
            Led4 <= temp(4);
            Led5 <= temp(5);
            Led6 <= temp(6);
            Led7 <= temp(7);
        end if;      
    end process;
     
end Behavioral;

And I get the error:

ERROR:Xst:827 - "C:/VHDL/Pulse_Duration.vhd" line 31: Signal count cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.



Can you please help me ?

Thank you

Anders

 

[TrickyDicky]

you cannot have two clocks in one process - FPGAs only support a single clock.
you will need to build a rising/falling edge detector in your code. You can do this by comparing a registered version of a signal to the unregistered version. This way you can check for rising or falling over the period of a clock cycle.

I also recommend you look into synchronising your button presses to the clock (to avoid metastability issues) and also button debouncing.

 

[shaiko]

As TrickyDicky noted - you must synchronize the button pushes to your system.
Also, because it takes time to establish a good galvanic contact when being pressed -the output may be glitchy. This effect is called: "bouncing".

In order to read only one actuation at a time - you'll probably have to design a debouncing logic circuit. Think of it as a logical schmitt trigger.

- - - Updated - - -

Read this please:
https://www.eewiki.net/display/LOGIC/Debounce+Logic+Circuit+(with+VHDL+example)