How to measure decap in spice simulation?

[niopium]

Hi All,

I need to measure intrinsic decap value between Vdd and Vss (power and ground) of IO cell through spice simulaiton.
So I perform ac analysis for the following two circuits:



Then calculate Cdecap = Cref*imag(V0)/imag(Vref).

Is it correct way do measure decap? If not then how should one measure decap?

Andrew

 

[crutschow]

It's unlikely that the Spice model would have accurate values for the device intrinsic capacitance between power and ground since that is not something normally of concern to a circuit designer. Why do you want that value?

 

[niopium]

I have to develop IBIS models and correlate them against spice, with non-ideal power network. As far as IBIS models do not pick up any data about Cdecap, I would like to add it directly. But first of all I need to extract it from spice netlist. Hence my question.

 

[Chethan]

Hi,

IBIS 5.0 has options for accurate power integrity simulation ie., gate modulation. Then why do you need to get the decap values for ur supplies.

 

[niopium]

Hi,

IBIS 5.0 has options for accurate power integrity simulation ie., gate modulation. Then why do you need to get the decap values for ur supplies.

As I understand, power-ground Cdecap has any effect if Power to ground voltage is changing: current from supply flows to recharge Cdecap. IBIS 5.0 structures (both isso_pu/pd and composite current) are extracted for steady state points, when power to ground voltage is constant, so Cdecap is not recharged and doesn't have any impact on IV, VT and IT characteristics. And then, when I simulate IBIS and spice models with non-ideal supply, spice model does have some decap which creates extra current branch when power-to-ground voltage is changing. IBIS models gate modulation options allow to adjust current consumed by driver in response to pg voltage change, but cdecap current is not induced. Please correct me if I am wrong