In my design, I have a 16-bit shift register. I simulated it in schematic, and there is no setup/hold time violation. But I don't know what is good strategy to do its layout to avoid any potential setup/hold time violation. Should I put each register as close as possible? Shoud I put buffer between each register. Thanks a lot!
For shift register design, setup time isn't a problem. And hold time is more important to pay attention on it. To avoid feedthru problem, it's better to insert some small delay between each register when you design it manually.