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how to make tool for place and route algoithm (KL)

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Newbie level 4
Feb 7, 2013
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hi I want to make KL- algorithm related tool, which will helps to solve place and route problem like wire delay...
I want to place GUI in form of CLB o/p. without applying and after applying algorithm

whats wrong with normal synthesis tools?

whats wrong with normal synthesis tools?

sir, I just want to design simple tool related to KL- algorithm, related to place and route in fpga not the synthesis tool. my problem is how to initiate and map the clb struture to the gui. Want to keep the algorithm in the back end and run simply any digitl circuit before applying algorithm and after applying algorithm.. so that components are placed efficiently over CLB some how ire delay ll be reduced.

What's wrong with normal place & route tools? ;-)

Also, you might want to ask this on xilinx / altera forum. You have more chance there on information + a reality check.
I took a look at the wiki on the KL -algorithm, it appears to be what Xilinx used on the old simulated annealing algorithm they used to use. Where they try to optimize the number of crossings between regions and then slice regions into smaller regions and minimize crossings at that level.

As a user of those tools, that algorithm doesn't work very well.
Thank you for the suggestion.. Can u pls tel me on which algorithm should i work for optimization purpose..which one is the latest algorithm ...the link to study the tool.

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Thank you for the guidance.

If you want to know the details, I suggest you ask Xilinx and Altera Directly.

But I can already guess the response.....

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