There are two aspects. One is theoretical aspect. For this you should consult CMOS VLSI design book by David Harris. For PMOS, it is Rp and Rp = 2*RN. But PMOSes are in parallel and you have to take it like a resistor network where PMOSes are in parallel.So that makes Rp = Rn/2 since 4 PMOSES are in parallel. In series there are 4 NMOSES and their effective resistance is 4*RN. Now to make it equal to effective RP = Rn/2, they need to sized up by a factor of 8 i.e., Rn/8 + Rn/8 + Rn/8 + Rn/8 = Rn/2. This is one choice of sizing.
If you are doing HSPICE simulation, these theoretical numbers are not accurate and you have to manually do hit and trial until you get equal rise and fall times.
1) The pull up time will be data dependent, i.e. you have to see how many PMOS are ON at a time. Worst case will be 0111 and best will be 0000
2) For pull down time, due to velocity saturation, the effective resistance of the Four series NMOS will be reduced, so you will not see a 4Rn but less may be 2.5Rn to 3Rn.
"2). For pull down time, due to velocity saturation, the effective resistance of the Four series NMOS will be reduced, so you will not see a 4Rn but less may be 2.5Rn to 3Rn. "
If transistors are in series, the effective Vds seen by each transistor will be less and hence they will have less velocity saturation and hence more current and hence resistance decreases.
Use the spice level netlist of the 4 i/p nand gate. Once you freeze on the rise time or fall time.. make the width of the PMOS or NMOS as a variable and sweep it in your spice simulation to match the risetime/falltime...