nashafi
Member level 1
Hi,
I have designed a MAP deocder architecture flow here at my research group. I am now exploring the option of giving it for commercial use. But i have no clue as how i can protect my VHDL code and still give some one some thign which they can use to target any FPGA platform or may be change and timing requirements etc.
I was thinking may be .edf file is an option. but is it secure or there is a way to get VHDL back from edf.
I would appreciate a discussuin on this issue. As it will help all new designers.
Thanks,
-Nauman
I have designed a MAP deocder architecture flow here at my research group. I am now exploring the option of giving it for commercial use. But i have no clue as how i can protect my VHDL code and still give some one some thign which they can use to target any FPGA platform or may be change and timing requirements etc.
I was thinking may be .edf file is an option. but is it secure or there is a way to get VHDL back from edf.
I would appreciate a discussuin on this issue. As it will help all new designers.
Thanks,
-Nauman