how to make code not readable ?
i have written a vhdl code , i want others to use it as a component but not able to read it (access the source) , what shall i do ?
i think if i could compile it in a library , my goal is achieved , but when i compile it in modelsim in my computer it is okay , but when i take it to other computer it is not working (says it is not bounded) !
any help ?
thanks in advance
omid
Hi
in which software you write your codes. you can synthesis your code then a file will generate in NGC format. you can use NGC file as black box in other codes. on your top module only thing that you need is that use an entity of your NGC and instantiate it.
Hi
in which software you write your codes. you can synthesis your code then a file will generate in NGC format. you can use NGC file as black box in other codes. on your top module only thing that you need is that use an entity of your NGC and instantiate it.
when i synthesis the instantiate file with ISE , it is ok .
but the problem is this :
in simulation with modelsim , in instantiation file , it says : it is not bounded (modelsim does not see the ngc file to reference it
now my problem is in simulation with NGC file !